1. Field of the Invention
The present invention relates to metal-gate MOS transistors and, more particularly, to a metal-gate MOS transistor and a method of forming the transistor with reduced gate-to-source and gate-to-drain overlap capacitance.
2. Description of the Related Art
A metal oxide semiconductor (MOS) transistor is a well-known semiconductor device which can be implemented as either an n-channel (NMOS) device or a p-channel (PMOS) device. A MOS transistor has spaced-apart source and drain regions, which are separated by a channel, and a gate that lies over, and is insulated from, the channel by a gate dielectric layer. A metal-gate MOS transistor is a type of MOS transistor that utilizes a metal gate and a high-k gate dielectric layer.
FIG. 1 shows a cross-sectional view that illustrates a prior-art metal-gate MOS transistor 100. As shown in FIG. 1, MOS transistor 100 includes a semiconductor body 110. Semiconductor body 110, in turn, includes a single-crystal-silicon substrate region 112, and a trench isolation structure 114 that touches substrate region 112.
In addition, semiconductor body 110 includes a source 120 and a drain 122 that each touch substrate region 112. The source 120 and drain 122 each has a conductivity type that is the opposite of the conductivity type of substrate region 112. Source 120 includes a lightly-doped region 120L, and a heavily-doped region 120H. Similarly, drain 122 includes a lightly-doped region 122L, and a heavily-doped region 122H. Further, substrate region 112 has a channel region 124 that lies between source 120 and drain 122.
As further shown in FIG. 1, MOS transistor 100 includes a high-k gate dielectric structure 126 that touches and lies over channel region 124, and a metal gate 130 that touches gate dielectric structure 126 and lies over channel region 124. MOS transistor 100 also includes a sidewall spacer 132 that touches gate dielectric structure 126 and laterally surrounds gate 130.
MOS transistor 100 additionally includes a non-conductive interconnect dielectric structure 138 that touches sidewall spacer 132 and lies over source 120 and drain 122. Dielectric structure 138 can be implemented with an etch stop layer 140 and a dielectric layer 142 that touches and lies over etch stop layer 140.
The threshold voltage of a transistor is the gate voltage required to form an inversion layer at the top surface of the channel region that is sufficient to allow a current to flow from the source region to the drain region. In the case of an NMOS transistor, n-type dopant atoms form the inversion layer, while p-type dopant atoms form the inversion layer in the case of a PMOS transistor.
In operation, with respect to NMOS transistors, when a positive drain-to-source voltage VDS is present, and the gate-to-source voltage VGS is more positive than the threshold voltage, the NMOS transistor turns on and electrons flow from the source region to the drain region. When the gate-to-source voltage VGS is more negative than the threshold voltage, the MOS transistor turns off and no electrons (other than a very small leakage current) flow from the source region to the drain region.
With respect to PMOS transistors, when a negative drain-to-source voltage VDS is present, and the gate-to-source voltage VGS is more negative than the threshold voltage, the PMOS transistor turns on and holes flow from the source region to the drain region. When the gate-to-source voltage VGS is more positive than the threshold voltage, the PMOS transistor turns off and no holes (other than a very small leakage current) flow from the source region to the drain region.
One of the problems with MOS transistor 100 is that high-k gate dielectric structure 126 substantially increases the gate-to-source and gate-to-drain overlap capacitance. Thus, there is a need for a metal-gate MOS transistor that reduces the gate-to-source and gate-to-drain overlap capacitance associated with a high-k dielectric structure.